1. Verilog Synthesis
Synthesize Verilog code using Yosys for various FPGA targets (generic, ice40, xilinx).
2. Verilog Simulation
Simulate designs using Icarus Verilog with automated testbench execution.
3. Waveform Viewing
Launch GTKWave for VCD file visualization and signal analysis.
4. ASIC Design Flow
Complete RTL-to-GDSII flow using OpenLane with Docker integration.
5. Layout Viewing
Open GDSII files in KLayout for physical design inspection.
6. Report Analysis
Read and analyze OpenLane reports for PPA metrics and design quality assessment.