A Model Context Protocol (MCP) server that integrates Electronic Design Automation (EDA) tools for AI assistants, enabling Verilog synthesis, simulation, ASIC design flows, and waveform analysis through natural language interaction.
Synthesize Verilog code using Yosys for various FPGA targets (generic, ice40, xilinx).
Simulate designs using Icarus Verilog with automated testbench execution.
Launch GTKWave for VCD file visualization and signal analysis.
Complete RTL-to-GDSII flow using OpenLane with Docker integration.
Open GDSII files in KLayout for physical design inspection.
Read and analyze OpenLane reports for PPA metrics and design quality assessment.
{
"mcpServers": {
"MCP_DOCKER": {
"command": "docker",
"args": [
"run",
"-i",
"--rm",
"alpine/socat",
"STDIO",
"TCP:host.docker.internal:8811"
]
},
"eda-mcp": {
"command": "node",
"args": [
"/absolute/path/to/your/eda-mcp-server/build/index.js"
],
"env": {
"PATH": "/usr/local/bin:/opt/homebrew/bin:/usr/bin:/bin",
"HOME": "/your/home/directory"
}
}
}
}